System to make VFO PLL (phase lock loop)

Homebrew multiband SSB transceiver part 5

The basis of the PLL circuit system can be described as below:


a. Frequency Reference
This circuit has a stable output so it should be raised through Xtal oscillator, which then split - for to obtain a low frequency such as 1 KHz. So F1 = 1kHz
b. Comparator:
This circuit has 2 input frequency F1 and F2 and have an output DC voltage. The nature of this circuit is: If F1 = F2 then the output is a constant DC voltage. And If F1 is not F2 is equal to the DC output is shaped sawtooth (saw tooth). Output voltage is fed to the VCO circuit.
c. VCO = Voltage Controll Oscilator:
This circuit is a series of Variable frequency oscillator which is controlled by frequencynya output voltage. In this PLL circuit that controls the voltage is voltage output of the Comparator. From the picture above if F1 = F2 = 1 KHz then the voltage output of Comparator constant so that the output frequency of VCO fixed or stable. In such circumstances This system is said in LOCK state.
d. PROGRAMMABLE DEVIDER:
This circuit is a circuit that can divide frequency, has an input and an output. TC9122 IC can be divided from 1 to 3999.
For this programming provided on 14 pin TC9122 for BCD numbers,
A1A2A3A4 B1B2B3B4 C1C2C3C4 D1D2.
If you want to deprogram the 3149 PIN 2 must be in give voltage:
1001 0010 1000 11.
1 = high (no tension) and 0 = low (no voltage)
If N is made 3149's F1 = 1 KHz the system in will LOCK when Fout = 3149 MHz. The formula is
Fout = N = Nx F1
divisor program, F1 = freq.Ref