In principle, Phase Lock Loop is a feedback control circuit system consists of main parts as follows:
1. Phase Detector
2. Loop Filter
3. Voltage Controlled Oscillator (VCO)
Major role in the PLL phase detector is held by the duty comparing the input phase of the VCO signal with a reference signal and the output is a different phase.
The existence of different phases will provide a further voltage difference, the difference voltage is filtered by the loop filter and applied to VCO. Then the control voltage to the VCO frequency change towards minimize the difference between a reference signal with a feedback signal from VCO. If the loop becomes locked, then control voltage in a position where the average frequency of feedback signal exactly equal to the frequency reference.
The success of a PLL design is largely determined by the loop filter design good. This is because in the event of phase difference, phase detector, voltage differences will issue a change up and down. Loop filter must be able to hold sway voltage so that voltage changes into the VCO becomes smooth.
Figure 1. PLL diagram
For the purposes of use as a regulator of the transceiver operating frequency,
various PLL can we make, but in this paper try asking a PLL design with a detailed circuit so that we can easily understand how it works. Although to fulfill that purpose is required of
many components, but with this design step can work clearly understood. In this design is used a lot of IC TC9122,TC5081, TC5082, TC4017 and TA7310.
Actually PLL circuit can be made with a fairly simple example using IC type MC145106, MC145163, and so forth there are also many on the market. These type of IC has been able to perform the function is complete, with an IC is able to perform the functions of the TC9122, TC5081, TC5082 and TC4017. But the use of IC type is not discussed in this paper.
Circuit Design
In this paper proposed a PLL design with step 1 KHz fine equipped with an analog tuner with band width of 1 to 2 KHz to allow setting more precise operating frequency (less than 1 KHz).
PLL is planned to be able to work from 13,700 to 14,699 MHz for use in transceiver with carrier oscillator or 10.7 MHz SSB filter. Working frequency is set with three-digit thumb wheel such that the number of hundreds, tens and units of KHz on the display thumb wheel can immediately show operating frequency transceiver.
If we have described, the PLL consists of several parts is generating reference frequency (1KHz), phase detector, loop filter, VCO, programmable oscillator mixing DEVIDER and feedback.
As a reference frequency generator used to charge TC5082 raised frequency of 10 KHz and the duty to share TC4017 frequency 10KHz results from TC5082 to 1KHz. 1KHz frequency is then used as comparison phase by phase detector TC5081.
For VCO in this design is used TA7310. The use of IC is intended to be at once doubled as the mixer for the purposes of feedback on the phase detector through a programmable DEVIDER. In this design the input to the programmable DEVIDER a result of the reduction of the frequency VCO with frequency crystal.
Frequency VCO and band width is set according to the needs in this design he should be able to work at a frequency of 13,700 MHz to 14,700 MHz, for used on instrument with 10.7 Mc IF. As a control frequency of the VCO varactor diodes are used. Various types of varactor can be used for example MV2205, MV2209, BA150, SMV 610 and so on. Type varactor diode of the above have a capacitance range different which can be seen in vademicum issued by the manufacturer.
Programmable devider share feedback from the VCO frequency by a factor of divider as we enter the program, the results are fed into the phase detector and compared with the reference signal. As a programmable DEVIDER TC9122 use, type of IC has the ability to share with the divisor factor until 3999.
Therefore, feedback from the VCO can not be directly input to TC9122 and must first be mixed with an oscillator frequency and the result is inputted into devider. Frekuensi mixer oscillator must be chosen so that the reduction does not exceed the ability of TC9122. For example, the PLL design is planned to work on 13,700 MHz to 14,699 MHz oscillator used mixing 12,700 MHz (the difference is 1-1999 MHz).
TC9122 programming done Binary coded Decimal (BCD) is that any decimal number represented by 4 binary digits. Entering unit numbers done by hand while the thousands (MHz) is permanently inserted directly connected pins 15 to Vdd. Entering done by thumb wheel, or can also use the Up down switch.
Up Down Switch for PLL
Frequency mixing crystal oscillator is selected on 12.700MHz with the intention that display numbers on the right thumb wheel with working frequency transceiver. For the purpose this often required a crystal with a frequency that is hard to find in the market. If no
crystals can be obtained with the ideal frequency as mentioned above, can also be selected crystals
with frequencies close to the consequences of viewing figures thumb wheel odds with the frequency of work.
Used as a phase detector IC TC5081 charge of comparing the phase feedback signal derived from the VCO through a programmable DEVIDER with reference signal.
The next phase detector will set the control voltage through the loop filter so that the VCO
adjust the frequency so that its phase equals with reference frequency.
In pin 4 of the TC5081 facility if there equipped with LED circuit indicator may give an indication whether the PLL in lock state or not. With the circuit as shown on the figure 2 above, the LED will light when the PLL is not locked in and will die if PLL locked.
Supply voltage electricity can be used with 5 to 9 VDC, this design used in +5 V. The use of higher supply of 5V on this design can be done without having to change the value of component values except elco and tantalum voltage that must be considered.
Reff. Sunarto YBOUSJ
