Homebrew 30Mhz Frequency Counter

Design tools that I created is based on an amateur radio OM3CPH, the site he was actually there are 2 kind of design are Seven segment display and LCD display. To save money so I select the design that using Seven segment display.
Construction: For Schematic, PCB and PIC source programs I use OM3CPH original design or can download here , for the power supply is very easy to make that could provided a stable 5V voltage to the PIC microcontroller, for box case can be made according to our tastes, of this I use acrilig formed sheet and the box cover use material from PCB sheet. Front panel of the box we can print with our personalizing , printing is made by computer and I stick with double-sided tape.



Peripheral: For the purposes of measurement must have a suitable probe, using probes with a length of cable as needed. To probe Conector ground used for the crocodile and measuring probes use the osiloscope probe but with a cheaper version.
Have Fun...

Making the VFO PLL for High Frequency

Homebrew multiband SSB transceiver part 6

Programmable IC TC 9122 DEVIDER was only able to divide frequency up to approximately 14 MHz at 6-volt voltage.
For the ability devider is 1 to 3999.
Therefore, if the frequency that must be shared exceeds the capacity it should be held down Conversion, which required pre-mixer.
For example the 5266 KHz IF frequency to be work in the 14250 KHz band is required to vfo frequency 14250 + 5266 = 19516 KHz PLL so must be made
who worked around 19516 KHz.

In this project the set Oscilator Reference 1KHz, was
Xtal oscillator taken 16 MHz. Because 16MHz crystal
available lots in the market.

From the block diagram above can be calculated that the frequency of
into the TC 9122 to work on 14250KHz is 19516KHz -16000KHz = 3516KHz. 3516 numbers are still under number 3999 of the divider TC 9122. So the 14250KHz working frequency must be programmed for the TC9122 to 3516 that if written in BCD: 11 0101 0001 0110
Control circuit used for IC CD4029 up / down counter that can be programmed.

To move UP / DOWN is used two IC CD4011 also as debouncer. Encoder dial can
use mechanical systems that available in the market. Dial encoder can be used from the component MOUSE computer unused / damaged.

To make the VFO on the other band, the market can be found in the crystal
with frequency 3, 5, 6, 8, 10 and 16 MHz that can be tried to achieve the desired frequency band

System to make VFO PLL (phase lock loop)

Homebrew multiband SSB transceiver part 5

The basis of the PLL circuit system can be described as below:


a. Frequency Reference
This circuit has a stable output so it should be raised through Xtal oscillator, which then split - for to obtain a low frequency such as 1 KHz. So F1 = 1kHz
b. Comparator:
This circuit has 2 input frequency F1 and F2 and have an output DC voltage. The nature of this circuit is: If F1 = F2 then the output is a constant DC voltage. And If F1 is not F2 is equal to the DC output is shaped sawtooth (saw tooth). Output voltage is fed to the VCO circuit.
c. VCO = Voltage Controll Oscilator:
This circuit is a series of Variable frequency oscillator which is controlled by frequencynya output voltage. In this PLL circuit that controls the voltage is voltage output of the Comparator. From the picture above if F1 = F2 = 1 KHz then the voltage output of Comparator constant so that the output frequency of VCO fixed or stable. In such circumstances This system is said in LOCK state.
d. PROGRAMMABLE DEVIDER:
This circuit is a circuit that can divide frequency, has an input and an output. TC9122 IC can be divided from 1 to 3999.
For this programming provided on 14 pin TC9122 for BCD numbers,
A1A2A3A4 B1B2B3B4 C1C2C3C4 D1D2.
If you want to deprogram the 3149 PIN 2 must be in give voltage:
1001 0010 1000 11.
1 = high (no tension) and 0 = low (no voltage)
If N is made 3149's F1 = 1 KHz the system in will LOCK when Fout = 3149 MHz. The formula is
Fout = N = Nx F1
divisor program, F1 = freq.Ref

Make Exciter SSB transceiver.

Homebrew multiband SSB transceiver part 4

In a box if there is a TX and a RX is the box can not be called an Transceiver (TRX). Because of a unit will be called a transceiver when the unit are Tx and RX. and between the TX and RX there some components such as IF amplifier combined, SSB filter, VFO, power supply and others.
In this project for good efficiency RF amplifiers for transmit and to receive also be incorporated. More and more components / units are held together more quickly and easy to assemble.
In this project is put together is:
a. Power Supply
b. If amplifier
c. SSB filter
d. VFO
e. RF amplifier TX / RX

Note that in this circuit there are many diodes , A few diodes act as switches and the other as DC current bloking.

Homebrew make IF transformer

Homebrew multiband SSB transceiver part 3

From the results of experiment for frequewncy around 5 MHz (5.2665MHz) L1 = L2 = 30 wrap 5 Koker wrap on the ferrite core diameter of 6 millim, C1 = 100 pf.
IF amplifier includes Low Power Amplifier so that only need a small current, and a parallel load L1C1 as a band pass filter.
We know that the LC parallel a high impedance, while the bipolar transistor has a medium impedance. As such collector can not be connected directly to point A but ketitik B, That be located where the question point B?
There Rule of Thumb is: Called hot-end point A, point C is called the cold-end if the collector higher impedance point B must be closer to point A. And vice versa if the impedance collector more Low point B closer to point C.
We know that the impedance Z = V / I with a large or small impedance depends on the size of collector currents collector. The smaller the current higher impedance.
The amount of L2 that will roll into the amplifier input The next approximately 1 / 6 of the number of coils L2 and must rolled near point C cold-end.

Make SSB Filter

Homebrew multiband SSB transceiver part 2

Experience shows that to make a SSB filter This is the most profitable is to configure Lattice Filter. With this configuration seems to be very easy to achieve a flat top on the pass band, and both have a slope of near symetris, so easy to use to filter the USB and LSB. In this project used two types of crystals each with a frequency X1 = X2 = 5.26665 and 5.26865 MHz.
Note that it has 2 crystal 2 KHz difference. LC components in parallel resonant frequency is set to 5.26765 to form near the top flat. Condensator C1 and C2 expected that the band pass filter becomes wider.


In this project C2 = 10 pf and R1 = R2 = 2.2k. LC1 set Resonant in the middle order bandpass peaks Bandpass near average. L Koker wound on ferrite core 6 mm as many as 45 wrap while C1 = 50 pf. There are several terms for this SSB filter,:
a. Band pass as shown symetris called filters, left and right slopes of the same
b. Boundary slope with flat line is notch filter. In image point X1 is X2 notch below being called top notch.
c. If the carrier frequency in the notch below ditepatkan there will be a SSB USB and vice versa if matched carrier frequency of the notch that will there is SSB LSB d. Thus to change from LSB to the USB is denganmengganti carrier frequency without having to replace filter.
This is one advantage of the filter that symetris.

Homebrew Multiband SSB Transceiver part 1

For radio amateurs who enjoy making their own equipment Sure hope some time to make homemade multiband transceiver. Here the author deliberately design a display-oriented SSB transceiver with components that are easy to make and with components easily available in the market. The block diagram of multiband transceiver like the following:

Figure 1 Multiband SSB Transceiver diagram

From the diagram above transceivers today I want to explain important points only gradually and is the key to the design, are:
1. Make a SSB filter
2. Creating IF amplifier transformers
3. Creating Exciter
4. Making the system PLL VFO for each band ( 3.5, 7, 14, 21, 28 MHz).
5. Creating the DDS VFO (Direct Digital Synthesizer)
6. Digital display.

Homebrew PLL for HF Band

This is a PLL design that have been tried and works well for HF bands,
based on this design can be developed more PLL for frequency other band.


1. Because this PLL works at 100 Hz step, it created the first reference frequency 100 Hz. Circuit that handles it is UNIT CLARIFIER, IC2, IC3, IC4 and IC5 is fed to the Comparator pin3. CLARIFIER produce 6144 MHz frequency changed by a digital signal IC2, IC3 divided by 4069 and divided again by 15 by IC4 thus obtained frequency 100Hz.
2. PLL design is the issue of output 5.5 MHz to 6 MHz.Output of VCO strengthened in addition to output, some output is inserted into IC1 Pin 4 to be mixed with the xtal oscillator frequency. The results of this mixing the difference is taken and converted into digital signals by the IC2 and fed to the IC19 (4059) called programmable DEVIDER.
3. In this project we design so that it is in the ON PLL's output frequency 5.7MHz. (Please design something different). The output of the mixer IC1 Pin6 is 6144 - 4440 = 5.7 Hz, which is then fed to the PROGRAMMABLE IC10 DEVIDER Pin1 for 4440 divided by the number 100 to get the results hz on pin 13. The output from IC 10 pin 13 is fed to the IC Comparator 5. Because IC5 receive 2 same frequency 100Hz then the IC 10 will be LOCK marked with LED flame. Pin output of Comparator 13 is a a constant DC voltage and fed to the varicap diode at 209 MV VCO. Thus the PLL out will also be constant or stable at 5.7MHz to Comparator LOCK, so that the output of IC5 is a DC voltage a constant and flat. This DC voltage is fed to the VCO so that the PLL stable at 5.7MHz frequency.
4. To program the IC 10 to divide the 4440, conducted via UP / DOWN consisting of counter IC6, IC7, IC8 and IC9, which each have Pin 4, 12, 13 and 3, which is used to enter the program. If PIN2 is given 9-volt voltage will have a weight like a table in the schema, while the foot that the weighted ground ZERO.
5. In this project programmed IC 6 weight 4, then 4000, weighing 7 IC 4 means 400, IC 8 weighted 4, means 40 are IC9 weighted 0, so the value of the program is = 4000 + 400 + 40 + 0 = 4440. (try it with other programs)
6. Dial Encoder with all its components to move the value of the program which is the UP / DWN counter so that the PLL to walk up / down.

Reff. Supardi yb3dd.

Digital decoder for PLL

In the example of the use of TTL IC this time, we will try to submit a design Switch to set UPDOWN operating frequency of a PLL which uses TC 9122. First we will take the IC 7400 to create two inputs to the flipflop as the following counter is 74192.

Figure 1.Updown digital switch

With the above design, when the UP button is pressed, IC1 will count forward, and the calculation results will be issued as a Binary coded Decimal via pin 3, 2, 6 and 7. If the count at IC1 has reached 10, it will give one IC1 to IC2 pulses that will calculate forward IC2 and IC1 ONE count back to ZERO. BCD output is then used as input to the PLL to adjust the working frequency.

Figure 2.Seven segment display

If the output is sampled and used as input to the IC 7447 to turn 7 segment, the results of this calculation can be displayed.

Mixer oscillator for PLL

If the crystals with the ideal frequency is not obtained, then another way to create a feedback oscillator is by mixing the two oscillators. Mixture can also be done by entering the Carrier Oscillator frequency of the plane into the mixer and mix it with 3 MHz crystal oscillator (This crystals are common in the market ). To make this mixer can be used MC1496 as Figure 1 and TA7310 the following Figure 2. If we compare between the two mixer, then a simpler circuit TA7310 and not a lot of eating places on the PCB.

Figure 1. MC1496 mixer


Figure 2.TA7310 PLL mixer

If colleagues have advanced radio amateurs to assemble this kind of PLL along with modifications, it will easily develop with such use types other ICs. In this paper described only single-loop PLL with fellow radio amateur colleagues can continue to develop such a double-loop PLL design so obtained lengkah smaller multi-KHz and the VCO can also be developed into multiband PLL. With a little knowledge about the use of TTL ICs, the tuning frequency can be done in other ways such as with the UP / DOWN switch or can be developed again by using the Rotary decoder circuit.

Component and PCB Design PLL

The type and number of components required for assembly PLL are given in Table 1 below and the layout of components on the PCB can be examined in Figure 1 and the PCB as shown in Figure 2.

List of components.
Component parts primarily to the circuit loop filter and VCO circuit Is C1, C2, C3 and C4 is preferable to use Condensator NPO type C3, while for more preferred tantalum.

Figure 1 Component layout PLL

Figure 2 PCB layout PLL

How to assembly

How to install the components on the PCB is recommended to use sequential order as the following :
1. Installation of voltage regulator
2. Installation of VCO and then in a state of components in other parts not yet installed pengecheckan held output at OUTPUT terminals. The frequency of the output should be located in between 13 ~ 14 MHz.
3. Installation of feedback oscillator, then the output frequency was observed at 3 and the TEST POINT fine tuner to start, he should be able to move between the frequency of up to 12,700 + 1KHz untill 12,700 - 1KHz.
4. Installation DEVIDER 1 (TC5082) and checked on the TEST POINT 1, the output frequency must exactly 10 KHz.
5. Installation DEVIDER 2 (TC4017) and checked on the TEST POINT 2, the output frequency must exactly 1 KHz.
6. Installation of programmable DEVIDER (TC9122) and the phase detector (TC5081). With all installed components, PLL must be locked in position thumb wheel or thumb wheel 000 not installed (LED should be extinguished). If not locked, then the L1 adjusted on ferrite so that the PLL can be locked.
7. Installation of thumb wheel and then dial 999 is placed in position, the LED should remain off, if not then the ferrite from the L1 reset. In other words the PLL to the design must can be locked from the frequency to 13,700 MHz to 14,699 MHz.
8. Furthermore thumb wheel 000 is set at the position, then dial the unit level increased by equivalent to the number 9 position as observed whether the increase of output frequency exactly 1 KHz. Unless appropriate increase the frequency of 1 KHz is not swayed. So done also for the tens dial and dial hundreds. Please note that each will hold a checking, always considered first whether the component is fully installed and already well construction. Important is whether the voltage at the IC pins and pad at the foot of the transistor is correct.

LC Resonance Circuit VFO

High frequency and low frequency limits of this work tend VFO determined by the value of L1 and C1 (check the circuit diagram in the figure 2 above),besides of course the use of varactor. Calculation for determine the amount of L1, C1 and varactor type used seemed too complicated. However, in practice we can expect roughly taking into account L1 and C1 alone and with trial and error method we develop some results so that getting what we want. To think big about inductance L1 with a capacitance C1 we have specify, you can use the following formula calc Resonance :
f is expressed in MHz
L is the inductance coil L1 is expressed in uH.
C is the capacitance C1 is expressed in pF.
For example in VCO design specified the desired resonant frequency 12.700MHz, while the value of 30 pF C1 is selected, then the calculation according to the formula above the value obtained L approximately 5 uH.
To make a coil with the above values should be some experiment. Based on the results of the experiment the author, when used Koker former radio IF as shown in Figure below with loops of wire Koker's former hair, then to be able to obtain the value approximately 5 uH 8T empirically necessary.

Figure IF coil

By rotating the coil ferrite is, the value will change the inductance that can be adjusted to obtain the correct value. Please note that not all Koker have the same properties, so depending on the type of ferrite used. Experiments in above is done by using IF Koker RCL brand shop that there are many in the market,with other types of Koker will get different results.

PLL Frequency Synthesizer Step 1 KHz

In principle, Phase Lock Loop is a feedback control circuit system consists of main parts as follows:

1. Phase Detector

2. Loop Filter

3. Voltage Controlled Oscillator (VCO)

Major role in the PLL phase detector is held by the duty comparing the input phase of the VCO signal with a reference signal and the output is a different phase.

The existence of different phases will provide a further voltage difference, the difference voltage is filtered by the loop filter and applied to VCO. Then the control voltage to the VCO frequency change towards minimize the difference between a reference signal with a feedback signal from VCO. If the loop becomes locked, then control voltage in a position where the average frequency of feedback signal exactly equal to the frequency reference.

The success of a PLL design is largely determined by the loop filter design good. This is because in the event of phase difference, phase detector, voltage differences will issue a change up and down. Loop filter must be able to hold sway voltage so that voltage changes into the VCO becomes smooth.

Figure 1. PLL diagram

For the purposes of use as a regulator of the transceiver operating frequency,

various PLL can we make, but in this paper try asking a PLL design with a detailed circuit so that we can easily understand how it works. Although to fulfill that purpose is required of

many components, but with this design step can work clearly understood. In this design is used a lot of IC TC9122,TC5081, TC5082, TC4017 and TA7310.

Actually PLL circuit can be made with a fairly simple example using IC type MC145106, MC145163, and so forth there are also many on the market. These type of IC has been able to perform the function is complete, with an IC is able to perform the functions of the TC9122, TC5081, TC5082 and TC4017. But the use of IC type is not discussed in this paper.

Circuit Design

In this paper proposed a PLL design with step 1 KHz fine equipped with an analog tuner with band width of 1 to 2 KHz to allow setting more precise operating frequency (less than 1 KHz).

PLL is planned to be able to work from 13,700 to 14,699 MHz for use in transceiver with carrier oscillator or 10.7 MHz SSB filter. Working frequency is set with three-digit thumb wheel such that the number of hundreds, tens and units of KHz on the display thumb wheel can immediately show operating frequency transceiver.

If we have described, the PLL consists of several parts is generating reference frequency (1KHz), phase detector, loop filter, VCO, programmable oscillator mixing DEVIDER and feedback.

As a reference frequency generator used to charge TC5082 raised frequency of 10 KHz and the duty to share TC4017 frequency 10KHz results from TC5082 to 1KHz. 1KHz frequency is then used as comparison phase by phase detector TC5081.

For VCO in this design is used TA7310. The use of IC is intended to be at once doubled as the mixer for the purposes of feedback on the phase detector through a programmable DEVIDER. In this design the input to the programmable DEVIDER a result of the reduction of the frequency VCO with frequency crystal.

Frequency VCO and band width is set according to the needs in this design he should be able to work at a frequency of 13,700 MHz to 14,700 MHz, for used on instrument with 10.7 Mc IF. As a control frequency of the VCO varactor diodes are used. Various types of varactor can be used for example MV2205, MV2209, BA150, SMV 610 and so on. Type varactor diode of the above have a capacitance range different which can be seen in vademicum issued by the manufacturer.

Programmable devider share feedback from the VCO frequency by a factor of divider as we enter the program, the results are fed into the phase detector and compared with the reference signal. As a programmable DEVIDER TC9122 use, type of IC has the ability to share with the divisor factor until 3999.

Therefore, feedback from the VCO can not be directly input to TC9122 and must first be mixed with an oscillator frequency and the result is inputted into devider. Frekuensi mixer oscillator must be chosen so that the reduction does not exceed the ability of TC9122. For example, the PLL design is planned to work on 13,700 MHz to 14,699 MHz oscillator used mixing 12,700 MHz (the difference is 1-1999 MHz).

TC9122 programming done Binary coded Decimal (BCD) is that any decimal number represented by 4 binary digits. Entering unit numbers done by hand while the thousands (MHz) is permanently inserted directly connected pins 15 to Vdd. Entering done by thumb wheel, or can also use the Up down switch.

Figure 2. Circuit PLL

Up Down Switch for PLL

Frequency mixing crystal oscillator is selected on 12.700MHz with the intention that display numbers on the right thumb wheel with working frequency transceiver. For the purpose this often required a crystal with a frequency that is hard to find in the market. If no
crystals can be obtained with the ideal frequency as mentioned above, can also be selected crystals
with frequencies close to the consequences of viewing figures thumb wheel odds with the frequency of work.
Used as a phase detector IC TC5081 charge of comparing the phase feedback signal derived from the VCO through a programmable DEVIDER with reference signal.
The next phase detector will set the control voltage through the loop filter so that the VCO
adjust the frequency so that its phase equals with reference frequency.
In pin 4 of the TC5081 facility if there equipped with LED circuit indicator may give an indication whether the PLL in lock state or not. With the circuit as shown on the figure 2 above, the LED will light when the PLL is not locked in and will die if PLL locked.
Supply voltage electricity can be used with 5 to 9 VDC, this design used in +5 V. The use of higher supply of 5V on this design can be done without having to change the value of component values except elco and tantalum voltage that must be considered.

Reff. Sunarto YBOUSJ